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TITLE

 

Senior ASIC Design Engineer

COMPANY

 

Fungible

LOCATION

 

Santa Clara, CA, US

Description

Central to our mission is a highly programmable chip. As a senior digital ASIC designer, you will be responsible for all aspects of digital SoC design, focusing on micro-architecture, RTL, verification, logic synthesis, and timing analysis to deliver a design meeting target power, performance and area goals.

Skills, Education, and Experience Required
  • BS and/or MS in Electrical Engineering or equivalent degree
  • 10+ years of RTL design and/or architecture experience
  • Technical leadership across PCIe system architecture and design a necessity
  • Proven track record with the definition and development of complex SoCs
  • In depth understanding of networking and system interface protocols and architectures
  • Experience with high performance (low latency, high bandwidth) design techniques
  • Understanding of low power microarchitecture techniques
  • Strong knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis
  • Self-motivated and able to work effectively both independently and in a team

Additional Success Factors
  • Experience with designing for security
  • Ability to proactively take on responsibilities and ready to work in a start-up environment

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