1. Maintain and develop current DDR234/LPDDR234 IP.
2. Deep research on current controller/PHY architecture and micro-architecture.
3. Solve the simulation/integration/timing issue from the customer.
4. Add features on current DDR IP and validate
5. Make documents – Diagram/table/description using word and visio.
1. Familiar with AXI/DDR(JEDEC)/DFI specification. B.S. or M.S. in EE or equivalent is required.
2. 3+ years of experience on digital design or verification.
3. Familiar with scripts – Perl and tcl.
4. Familiar with timing concept and SDC.
5. Highly organized and self-motivated.
6. Ability to work with teammates.
7. Good language and communication skills in English for both spoken and written.