1. Responsible for the development and support of customer based design from netlist to GDS tape out, including:
2. ASIC floor plan or complex block (CPU/GPU..) implementation;
3. CTS, Power plan, Placement & Routing, SPF extraction;
4. Whole chip DRC/LVS, and GDS tape out
1. 3-5 years of experience and minimum of BS in EE or equivalent; MS a plus. Experienced in one of the major P&R (Place & Route) tool suites (Cadence, Synopsys).
2. Background in timing closure and signoff (PrimeTime experience).
3. Scripting expertise (Perl, Tcl, or Python) a strong plus.
4. Actual chip tapeout experience on a recent technology node (40nm or below) a strong plus.