1. Be responsible for synthesis, formal verification, static timing analysis and low-power check of SoC and blocks.
2. Work with back-end engineers to work on timing convergence and necessary ECO.
1. BS/MS+ in EE required.
2. More than 2 years experience in IC implementation.
3. Familiar with SoC implementation flow, good timing convergence experience and ECO experience.
4. Be familiar with EDA tools of Synopsys/Cadence/Mentor.
5. Be familiar with linux/unix environment and Perl/Tcl.
6. Familiar with SoC design and back-end design is preferred.
7. Good teamwork spirit and communication skills, responsible attitude.