1. Build SoC verification environment with UVM methodology, set up the verification plan.
2. Write test cases, analyze simulation results, improve verification quality.
3. be responsible for verification of IP level, top level, pre-sim, post-sim.
4. Be responsible for chip tape-out quality and increase the accumulation of verification knowledge for the team.
1. More than 2 years experience in IC verification
2. Be familiar with chip design flow and UVM methodology, have experience in writing test cases in UVM environment.
3. Be familiar with EDA tools of Synopsys/Cadence
4. Be familiar with linux/unix environment and perl/python.
5. Be familiar with assembler language, C/C++, have experience in writing test cases with them.
6. Be creative, ready for challenge, be good at cooperating with other team members.
7. Good English reading and writing ability.