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TITLE

 

Senior ASIC Physical Design Methodology and Flow Development Engineer

COMPANY

 

Fungible

LOCATION

 

Santa Clara, CA, US

Description

As a member of Fungible's physical design team you will be responsible for defining and developing solutions for end to end, physical design flow, methodology of high performance chips. The candidate will develop and qualify the methodology and implementation flow in advanced technologies like 16nm/14nm/7nm/5nm. The candidate will be working closely with the Physical Design Team, tool and fab vendor. This position requires in-depth understanding of the physical design flow, advanced design rules, DFM, timing closure, thermal and reliability analysis. Hands-on flow development and scripting is required.

Skills, Education, and Experience Required

  • BS or MS in Electrical Engineering or equivalent degree
  • 10+ years of experience in ASIC Physical Design from RTL to GDSII
  • Strong experience in Physical Design – place and route; Floorplanning; Power Analysis – IR Drop and EM analysis
  • Strong skills in Physical Verification (DRC/LVS/ERC/ANT) with digital and mixed-signal designs
  • Strong Timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding
  • Strong scripting experience in Perl and TCL
  • Working experience on CAD tools from Synopsys, and Cadence and 16nm/14nm process technology
  • Must be a self-starter, and be able to independently and efficiently drive tasks to completion

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