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Senior Fullchip Physical Design/Integration Engineer






Santa Clara, CA, US


Your primary job responsibility is to perform physical design from netlist to GDS. You will be working in a challenging but rewarding environment where we are pushing the limit on performance, power, and area with a very talented team.

Tasks to include chip and/or block level floor planning, bus / pin planning, power planning, clock tree synthesis, placement, optimization, routing, parasitic extraction, static timing analysis, IR drop analysis, physical verification and sign off. Hands-on flow development and scripting is required.
Skills, Education, and Experience Required 
  • BS or MS in Electrical Engineering or equivalent degree
  • 10+ years of experience in ASIC Physical Design from RTL to GDSII
  • Strong experience in physical design – place and route; floorplanning; power analysis – IR drop and EM analysis
  • Strong skills in physical verification (DRC/LVS/ERC/ANT) with digital and mixed-signal designs
  • Strong timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding
  • Strong scripting experience in Perl and TCL
  • Working experience on CAD tools from Synopsys, and Cadence and 16nm/14nm process technology
  • Must be a self-starter, and be able to independently and efficiently drive tasks to completion

Apply for the job

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