1. At least 3 or more years of RTL level digital design experience with MS in EE or related (more senior levels will also be considered)
2. Willing to work as an active team player with group’s goal in mind.
3. Experience in writing simple digital models or real number models for analog IPs
4. Knowledge with process and device physics is a plus
5. Acceptable communication skill in written and spoken English
1. Provide digital design support to complete mixed signal IP.
2. Perform mixed-signal co-simulations to ensure accurate block level functionality with integrated analog circuits.
3. Logic Synthesis, Static Timing Analysis and Logic Equivalency Checking
4. Design for test, scan insertion, ATPG, Functional Test Vectors
5. Interface with Place and Route Engineering to perform timing check and back-annotated simulations.
6. Ensure database integrity before any release.
7. Execute any project assignment in the timing manner.
8. Follow company’s quality standards during any project execution.