1. Responsible for the development and support of customer based design form netlist to GDS tape out;
2. Responsible for VLSI chip floor plan;
3. Responsible for CTS, Power plan, Placement & Routing, SPF extraction;
4. Responsible for whole chip DRC/LVS, and GDS tape out.
1. 3+ years of experience and minimum of BS in EE or equivalent; MS is a plus. Experienced in one of the major P&R (Place & Route) tool suites (Cadence, Synopsys,
Mentor, or Magma);
2. Background in timing closure and signoff (PrimeTime experience);
3. Scripting expertise (Perl, Tcl, or Python) a strong plus;
4. Actual chip tapeout experience on a recent technology node (65nm or below) a strong plus.